US Patent 10573605 Layout-driven method to assess vulnerability of ICs to microprobing attacks

A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.