US Patent 11038701 Method for securing an integrated circuit during fabrication

The invention relates to a method of securing an integrated circuit during its fabrication on a wafer, said method including the following steps:delimitation of said wafer of the integrated circuit (1) into a first zone called a standard zone (5a) and a second zone called a security zone (5b), andcreation of a random connection tracks network (7b) in said security zone (5b) configured to interconnect a set of conducting nodes (9b) thus forming a physical unclonable function modelled by random electrical continuity that can be queried through said set of conducting nodes using a challenge-response authentication protocol.