US Patent 11043986 Reduction of cross-capacitance and crosstalk between three-dimensionally packed interconnect wires

A mesh interconnect interface includes a dielectric slice; first micro-bumps aligned along a longitudinal axis and positioned closest to a driver bank, which is to be coupled to a first mesh stop of a first chiplet; second micro-bumps similarly aligned and positioned farthest from the first driver bank; third micro-bumps similarly aligned and positioned closest to a second driver bank, which is to be coupled to a second mesh stop of a second chiplet; fourth micro-bumps similarly aligned and positioned farthest from the second driver bank, wherein the longitudinal axis is orthogonal to a gap between the chiplets. The groups of micro-bumps are disposed on the slice. A first group of wires are embedded in the slice to couple the first and second micro-bumps. A second group of wires are interleaved with the first group of wires and embedded in the slice to couple the second and third micro-bumps.