US Patent 9564908 Digital phase-locked loop and method of operating the same

Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.