List of Esilicon patents

Patents where

Current Assignee

Name

Esilicon

Name	Description	Patent Applicant	Current Assignee	Patent Jurisdiction	Patent Number	Date of Patent
‌ US Patent 9727681 Generating specific memory models using generic memory models for designing memories in VLSI design	Patent 9727681 was granted and assigned to Esilicon on August, 2017 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9727681	August 8, 2017
‌ US Patent 9460256 Integrated circuit design scaling for recommending design point	Patent 9460256 was granted and assigned to Esilicon on October, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9460256	October 4, 2016
‌ US Patent 9460255 Scaling of integrated circuit design including logic and memory components	Patent 9460255 was granted and assigned to Esilicon on October, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9460255	October 4, 2016
‌ US Patent 10554449 Baseline wander compensation in SerDes transceivers	Patent 10554449 was granted and assigned to Esilicon on February, 2020 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	10554449	February 4, 2020
‌ US Patent 9762261 Error detection and correction in ternary content addressable memory (TCAM)	Patent 9762261 was granted and assigned to Esilicon on September, 2017 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9762261	September 12, 2017
‌ US Patent 10454491 Successive approximation register (SAR) analog to digital converter (ADC) with partial loop-unrolling	Patent 10454491 was granted and assigned to Esilicon on October, 2019 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	10454491	October 22, 2019
‌ US Patent 9727682 Designing memories in VLSI design using specific memory models generated from generic memory models	Patent 9727682 was granted and assigned to Esilicon on August, 2017 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9727682	August 8, 2017
‌ US Patent 9852250 Memory optimization in VLSI design using generic memory models	Patent 9852250 was granted and assigned to Esilicon on December, 2017 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9852250	December 26, 2017
‌ US Patent 9435846 Testing of thru-silicon vias	Patent 9435846 was granted and assigned to Esilicon on September, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9435846	September 6, 2016
‌ US Patent 9263409 Mixed-sized pillars that are probeable and routable	Patent 9263409 was granted and assigned to Esilicon on February, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9263409	February 16, 2016
‌ US Patent 9711220 Duo content addressable memory (CAM) using a single CAM	Patent 9711220 was granted and assigned to Esilicon on July, 2017 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9711220	July 18, 2017
‌ US Patent 9454636 Integrated circuit design optimization	Patent 9454636 was granted and assigned to Esilicon on September, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9454636	September 27, 2016
‌ US Patent 9460257 Scaling of integrated circuit design including high-level logic components	Patent 9460257 was granted and assigned to Esilicon on October, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9460257	October 4, 2016
‌ US Patent 9454628 Scaling memory components of integrated circuit design	Patent 9454628 was granted and assigned to Esilicon on September, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9454628	September 27, 2016
‌ US Patent 9461000 Parallel signal via structure	Patent 9461000 was granted and assigned to Esilicon on October, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9461000	October 4, 2016
‌ US Patent 9460254 Scaling logic components of integrated circuit design	Patent 9460254 was granted and assigned to Esilicon on October, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9460254	October 4, 2016
‌ US Patent 9529669 Error detection and correction in binary content addressable memory (BCAM)	Patent 9529669 was granted and assigned to Esilicon on December, 2016 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9529669	December 27, 2016
‌ US Patent 9984997 Communication interface architecture using serializer/deserializer	Patent 9984997 was granted and assigned to Esilicon on May, 2018 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	9984997	May 29, 2018
‌ US Patent 10050003 Elongated pad structure	Patent 10050003 was granted and assigned to Esilicon on August, 2018 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	10050003	August 14, 2018
‌ US Patent 10018670 Wireless probes	Patent 10018670 was granted and assigned to Esilicon on July, 2018 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	10018670	July 10, 2018
‌ US Patent 10032516 Duo content addressable memory (CAM) using a single CAM	Patent 10032516 was granted and assigned to Esilicon on July, 2018 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	10032516	July 24, 2018
‌ US Patent 10469096 Successive approximation register (SAR) analog to digital converter (ADC) with partial loop-unrolling	Patent 10469096 was granted and assigned to Esilicon on November, 2019 by the United States Patent and Trademark Office.	Esilicon	Esilicon	United States Patent and Trademark Office	10469096	November 5, 2019

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