SBIR/STTR Award attributes
Quantum circuits operating at 20 mK are controlled by room temperature electronics, which are bulky and not scalable. These control electronics are connected to the quantum circuits using coaxial cables adding to the system thermal noise and increasing the latency of the quantum computations. A cryogenic control panel at <4 K and physically closer to qubits will solve these issues. There are multiple approaches to address the cryogenic logic, but the problem of cryogenic memory remains unsolved. Without a cryogenic memory, ongoing attempts to increase qubits will lead to a “cryogenic memory wall” for quantum systems, where processing will be restricted by the narrow bandwidth afforded by limited co-axial cables. As the United States government and private companies race towards bigger and more practical quantum computers, the importance of quantum system control will become crucial. An efficient cryogenic control panel with non-volatile memory will provide a strategic edge to domestic quantum technologies aiming for the quantum advantage. It is without a doubt that the DOE’s investments in quantum hardware will benefit from a cryogenic non-volatile memory. It will also assist other DOE QIS threads including quantum timing, sensing, and communications as well as high energy physics (HEP) applications. Cerfe Labs spun out from Arm Holdings to commercialize a novel memory technology (CeRAM) based on correlated electron materials. In phase I, Cerfe Labs has demonstrated the first sub-1 K non-volatile memory that is compatible with CMOS processing and meets quantum computers requirements. As a proof of concept, we fabricated CeRAM devices (5 and 10 µm) using spin-on deposition and tested them using DC sweeps as well as microsecond pulses at varying temperatures from 300 K down to 870 mK. As expected from the correlated electron materials physics, the devices showed good performance across the wide temperature range. We successfully operated devices for up to 1000 cycles without damage and retained the memory state for more than 12 hours, exhibiting CeRAM’s non-volatile behavior. In phase II, we plan to optimize the memory for the cryogenic operation including magnetron sputtering for higher quality films that will enable smaller device sizes, lower power and higher speed operations, array development, and packaging suitable for cryogenic temperatures. With initial data from phase II, we plan to engage customers (private and government) in the co-development of cryogenic memory to meet the requirement of specific quantum technologies. At the end of phase II, we will have a fabrication process that will be compatible and can be transferred to the fabrication facility. A successful DOE QIS-focused program allows us to mature our technology at larger dimensions and lower bit counts required by the QIS, and then proceed towards a much higher memory density demanded by commercial applications such as embedded processor memory and stand-alone non-volatile memory. Our first QIS product (phase III) will be a 16 kb memory for storing quantum gate waveforms, addresses, and other control instructions. With continued development, we plan to further increase the cryogenic memory density for implementing error corrections and other advanced quantum algorithms.
