SBIR/STTR Award attributes
Air Force requirements to hold critical targets at risk and to operate in A2/AD environments pose significant challenges driving sensor research and development. The problem is that as sensors get better, they generate more data and demand faster, more complex processing. AFRL and industry are pursuing: 1) reducing CSWaP for deployment on smaller, tactical, attritable penetrating weapon systems such as LCAAT; 2) achieving multi-mode functionality so that fewer sensors and platforms are needed for a given mission set; and 3) integrating with existing sensor systems such as the MS-177 for more rapid transition to Warfighting roles using traditional ISR platforms. DEC leveraged hardware from the successful AFRL High-Speed Storage Enclosure (HiSE) program to conduct proof-of-concept CSAAPS experiments. The architecture we used for Proof-of-Concept Experiments can meet CSAAPS requirements by aggregating six Modules into a 12U 19” Rack System. We have already demonstrated ~20 GB/s storage rates and 72 TB of storage. This architecture has plenty of headroom for firmware processing expansion, as it used less than 21% of the total FPGA resources and less than 56% of the highest used resource, block RAM. The available FPGA resources make it possible to exploit the commonality between SAR and SAL processing to develop an integrated SAR/SAL common processor capable of supporting both modalities as well as distinctive modes of each. Many other real-time techniques are also possible. During CSAAPS Phase II, we will integrate new firmware to double throughput and also enable full duplex I/O. We will integrate COARPs and OMS software to simplify integration with existing AFLCMC systems. Finally, we will design a 6U VPX embedded version of the system for deployed applications such as on aircraft.
