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Digital Optics Technologies, Inc. SBIR Phase II Award, August 2021

A SBIR Phase II contract was awarded to Digital Optics Technologies, Inc. in August, 2021 for $749,989.0 USD from the U.S. Department of Defense and United States Air Force.

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sbir.gov/node/2160869
Is a
SBIR/STTR Awards
SBIR/STTR Awards

SBIR/STTR Award attributes

SBIR/STTR Award Recipient
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Digital Optics Technologies, Inc.
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Government Agency
U.S. Department of Defense
U.S. Department of Defense
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Government Branch
United States Air Force
United States Air Force
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Award Type
SBIR0
Contract Number (US Government)
FA9550-21-C-00030
Award Phase
Phase II0
Award Amount (USD)
749,9890
Date Awarded
August 1, 2021
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End Date
August 1, 2023
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Abstract

We will develop a three-axes superluminal inertial measurement unit (SIMU), employing three chip-scale superluminal ring laser gyroscopes and accelerometers (SRLGA). Each SRLGA will make use of miniature Rubidium vapor cells, and integrated photonic technology (IPT) based components. The IPT components include narrow-band lasers, detectors, low-loss waveguides, and magneto-optic isolators, integrated on a single chip, operating at 780/795 nm. AlGaAsP Quantum Wells (QWs) will enable the realization of the active photonic components. In sections for the passive components, the QWs would be disordered to minimize optical losses. A resonator containing two miniature vapor cells will be used as the cavity for the two superluminal ring lasers, the beat-note between which will yield the rotation rate. One of the mirrors for the cavity will be mounted on a metallic diaphragm for accelerometry. The chip-mounted components will be interconnected with the cavity, as well as additional electronics on a printed circuit board, for off-set phase locking of lasers, locking to atomic transitions, and processing of rotation and acceleration data. During Phase I, we have established the feasibility of developing the necessary IPT components, including demonstrations of lasers, waveguides and detectors, thus paving the way for realizing the chip-scale SRLGA and the SIMU during

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