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Hong Kim

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Patent primary examiner of
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US Patent 7089296 System and method for caching and validating user and command specific server response messages
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US Patent 7089357 Locally buffered cache extensions having associated control parameters to determine use for cache allocation on subsequent requests
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US Patent 7089447 Apparatus and method for compression based error correction procedure in a data processing system
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US Patent 7093037 Generalized queue and specialized register configuration for coordinating communications between tightly coupled processors
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US Patent 7096330 Symmetrical data change tracking
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US Patent 7099875 Method and apparatus for making independent data copies in a data processing system
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US Patent 7100019 Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values
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US Patent 7103709 Retrieving device and method, recording medium, and program for enabling a plurality of associative memories for retrieval and auto-storing
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US Patent 7103733 Computer system obtaining information on capacity and usage of an area used by a computer and notifying the computer the status thereof
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US Patent 7103742 Burst/pipelined edo memory device
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US Patent 7103790 Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data
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US Patent 7103793 Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad
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US Patent 7107403 System and method for dynamically allocating cache space among different workload classes that can have different quality of service (QoS) requirements where the system and method may maintain a history of recently evicted pages for each class and may determine a future cache size for the class based on the history and the QoS requirements
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US Patent 7107415 Posted write buffers and methods of posting write requests in memory modules
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US Patent 7111132 Parallel processing apparatus, system, and method utilizing correlated data value pairs
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US Patent 7111133 Control apparatus for selectively operating with program data from two memories and having a system controller supplying program data and address for writing the data to the second memory
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US Patent 7111153 Early data return indication mechanism
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US Patent 7117316 Memory hub and access method having internal row caching
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US Patent 7120651 Maintaining a shared cache that has partitions allocated among multiple nodes and a data-to-partition mapping
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US Patent 7120715 Priority arbitration based on current task and MMU
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US Patent 7124256 Memory device for burst or pipelined operation with mode selection circuitry
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US Patent 7124269 Memory controller including data clearing module
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US Patent 7127480 System, method and program for backing up a computer program
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US Patent 7133969 System and method for handling exceptional instructions in a trace cache based processor
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US Patent 7143228 Storage control system and method for storing block level data in internal or external storage control system based on control information via networks
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US Patent 7149859 Method and apparatus for data migration with the efficient use of old assets
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US Patent 7151921 Management apparatus, management system, management method, and management program for memory capacity of mobile terminals
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US Patent 7152184 Storage device, backup method and computer program code of this storage device
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US Patent 7159139 Digital data storage subsystem including directory for efficiently providing formatting information for stopped records and utilization of a check value for verifying that a record is from a particular storage location
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US Patent 7162590 Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion
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US Patent 7162608 Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element
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US Patent 7168070 Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer
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US Patent 7171522 Storage system including storage adaptors having cache memories and grasping usage situation of each cache memory and equalizing usage of cache memories
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US Patent 7177975 Card system with erase tagging hierarchy and group based write protection
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US Patent 7177983 Managing dirty evicts from a cache
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US Patent 7177986 Direct access mode for a cache
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US Patent 7178002 Methods and systems for dynamically growing multiple stacks
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US Patent 7185020 Generating one or more block addresses based on an identifier of a hierarchical data structure
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US Patent 7190284 Selective lossless, lossy, or no compression of data based on address range, data type, and/or requesting agent
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US Patent 7200069 Semiconductor memory device having external data load signal synchronous with data strobe signal and serial-to-parallel data prefetch method thereof
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US Patent 7206902 System, apparatus and method for predicting accesses to a memory
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US Patent 7210023 Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address
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US Patent 7213101 Classless interdomain routing using binary content addressable memory having mask bits and mask valid bits
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US Patent 7213103 Accessing data storage systems without waiting for read errors
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US Patent 7213117 1-chip microcomputer having controlled access to a memory and IC card using the 1-chip microcomputer
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US Patent 7216201 Parallel cachelets
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US Patent 7216218 Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
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US Patent 7219192 Storage system and method for a storage control apparatus using information on management of storage resources
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US Patent 7219214 Data processing apparatus and method for moving data elements between a chosen lane of parallel processing in registers and a structure within memory
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US Patent 7219215 Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory
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US Patent 7222142 Methods and systems for moving data objects utilizing data identifiers and lock objects
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US Patent 7225303 Method and apparatus for accessing a dynamic memory device by providing at least one of burst and latency information over at least one of redundant row and column address lines
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US Patent 7233976 Cache slot lock for multi-thread file request
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US Patent 7243208 Data processor and IP module for data processor
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US Patent 7251663 Method and apparatus for determining if stored memory range overlaps key memory ranges where the memory address space is organized in a tree form and partition elements for storing key memory ranges
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US Patent 7254688 Data processing apparatus that shares a single semiconductor memory circuit among multiple data processing units
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US Patent 7257129 Memory architecture with multiple serial communications ports
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US Patent 7260613 Storage system, disk control cluster including channel interface units, disk interface units, local shared memory units, and connection portions, and a method of increasing of disk control cluster
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US Patent 7260679 Apparatus and method to manage a data cache using a first and second least recently used list
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US Patent 7260684 Trace cache filtering
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US Patent 7284088 Methods of reading and writing data
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US Patent 7287103 Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes
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US Patent 7290094 Processor, data processing system, and method for initializing a memory block to an initialization value without a cache first obtaining a data valid copy
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US Patent 7290120 Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer
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US Patent 7293194 Method and device for switching database access part from for-standby to currently in use
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US Patent 7299316 Memory flash card reader employing an indexing scheme
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US Patent 7299322 Computer system, storage device and method providing intra-storage volume identifiers corresponding to intra-host volume identifiers through volume switching commands
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US Patent 7302522 Optimizing I/O performance in a RAID subsystem using an adaptive maximum request size for a logical drive
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US Patent 7308539 Concurrent read access and exclusive write access to data in shared memory architecture
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US Patent 7313683 Computer system and method which boots from a bootup-memory-image stored in nonvolatile memory and copies data within an address range of predetermined width to main memory so that the system boots quickly after initialization
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US Patent 7318117 Managing flash memory including recycling obsolete sectors
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US Patent 7318133 Method and apparatus for replicating volumes
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US Patent 7318136 Method and apparatus implementing virtualization for data migration with the efficient use of old assets
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US Patent 7320049 Detection circuit for mixed asynchronous and synchronous memory operation
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US Patent 7330954 Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices
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US Patent 7330995 Nonvolatile memory apparatus which prevents destruction of write data caused by power shutdown during a writing process
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US Patent 7334063 Method and device for register access according to identifier register
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US Patent 7337264 Storage control system and method which converts file level data into block level data which is stored at different destinations based on metadata of files being managed
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US Patent 7337269 Method of managing a data storage array, and a computer system including a raid controller
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US Patent 7346736 Selecting basis functions to form a regression model for cache performance
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US Patent 7346740 Transferring speculative data in lieu of requested data in a data transfer operation
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US Patent 7366846 Redirection of storage access requests
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US Patent 7366847 Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag
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US Patent 7366871 Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table
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US Patent 7366882 Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions
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US Patent 7373480 Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table
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US Patent 7380064 Storage device and storage device data life cycle control method
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US Patent 7380093 Storage system including a device, data management unit, control unit and/or primary computer, and method, for allocating storage area
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US Patent 7383416 Method for setting a second rank address from a first rank address in a memory module
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US Patent 7398355 Avoiding locks by transactionally executing critical sections
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US Patent 7401191 System and method for performing disk write operations by writing to a data depot prior to an in-place write
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US Patent 7421535 Method for demoting tracks from cache
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US Patent 7426607 Memory system and method of operating memory system
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US Patent 7430632 Data management apparatus and method for determining a response time in flash memory devices
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US Patent 7436728 Fast random access DRAM management method including a method of comparing the address and suspending and storing requests
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US Patent 7437512 Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
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US Patent 7441138 Systems and methods capable of controlling multiple data access using built-in-timing generators
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US Patent 7447863 Storage resource management system, method, and computer for dividing volumes based on priority, necessary capacity and volume characteristics
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US Patent 7451295 Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues
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US Patent 7453752 Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder
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US Patent 7454558 Non-volatile memory with erase block state indication in data section
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US Patent 7454571 Heuristic cache tuning
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US Patent 7457909 Controlling operation of flash memories
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US Patent 7457920 Method and system for cache eviction
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US Patent 7461196 Computer system having an expansion device for virtualizing a migration source logical unit
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US Patent 7464223 Storage system including storage adapters, a monitoring computer and external storage
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US Patent 7467280 Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
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US Patent 7475169 Storage control system and method for reducing input/output processing time involved in accessing an external storage subsystem
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US Patent 7477578 Disk recording device and disk recording method for recording and erasing titles on a disk
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US Patent 7478119 System and method for transposing memory patterns within the physical memory space
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US Patent 7478206 Information-processor for controlling a storing area in accordance with an amount of requested information
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US Patent 7478216 Method, system, and article of manufacture for returning physical volumes
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US Patent 7478218 Adaptive cache sizing based on monitoring of regenerated and replaced cache entries
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US Patent 7480771 Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
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US Patent 7484042 Data processing system and method for predictively selecting a scope of a prefetch operation
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US Patent 7487297 Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system
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US Patent 7487321 Method and system for memory leak detection
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US Patent 7490214 Relocating data from a source page to a target page by marking transaction table entries valid or invalid based on mappings to virtual pages in kernel virtual memory address space
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US Patent 7493452 Method to efficiently prefetch and batch compiler-assisted software cache accesses
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US Patent 7496726 Controlling contention via transactional timers among conflicting transactions issued by processors operating in insistent or polite mode
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US Patent 7502813 Software update process using an extra memory block
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US Patent 7509329 Technique for accelerating file deletion by preloading indirect blocks
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US Patent 7512739 Updating a node-based cache LRU tree
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US Patent 7515987 Media library assembly having first data transfer assembly that receives first command signal and transmits second command signal to second data transfer assembly to decrease time-to-data
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US Patent 7516281 On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes
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US Patent 7519774 Data processor having a memory control unit with cache memory
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US Patent 7523267 Method for ensuring fairness among requests within a multi-node computer system
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US Patent 7523319 System and method for tracking changed LBAs on disk drive
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US Patent 7523320 Fiscal data recorder with protection circuit and tamper-proof seal
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US Patent 7529896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules
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US Patent 7529904 Storing location identifier in array and array pointer in data structure for write process management
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US Patent 7543273 Systems and methods for dynamic control of cache and pool sizes using a batch scheduler
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US Patent 7565503 Method and apparatus implementing virtualization for data migration with volume mapping based on configuration information and with efficient use of old assets
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US Patent 7568075 Apparatus, system and method for making endurance of storage media
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US Patent 7590805 Monitor implementation in a multicore processor with inclusive LLC
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US Patent 7593975 File system defragmentation technique to reallocate data blocks if such reallocation results in improved layout
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US Patent 7603538 Access environment construction system and method
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US Patent 7631152 Determining memory flush states for selective heterogeneous memory flushes
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US Patent 7631220 Method and system for completing a backup job that was interrupted during a backup process
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US Patent 7634626 Remote copy system
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US Patent 7634627 System and method for performing extent level backups that support single file restores
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US Patent 7634708 Relocatable storage protect keys for system main memory
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US Patent 7636826 Systems and methods for locking and exporting the locking of a removable memory device
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US Patent 7640366 Storage controller to control access to storage device via serial communication unit by executing control step units
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US Patent 7644149 Method of reflecting on another device an addition to a browser cache on a handheld electronic device, and associated device
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US Patent 7647456 Comparing data in a new copy relationship to data in preexisting copy relationships for defining how to copy data from source to target
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US Patent 7650465 Micro tag array having way selection bits for reducing data cache access power
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US Patent 7653796 Information recording medium and region management method for a plurality of recording regions each managed by independent file system
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US Patent 7657697 Method of controlling a semiconductor memory device applied to a memory card
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US Patent 7657701 System and method of flash memory wear leveling using distributed write cycles
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US Patent 7657702 Partial block data programming and reading operations in a non-volatile memory
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US Patent 7657706 High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory
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US Patent 7657708 Methods for reducing data cache access power in a processor using way selection bits
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US Patent 7657717 Coherently sharing any form of instant snapshots separately from base volumes
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US Patent 7673109 Restricting type access to high-trust components
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US Patent 7680980 Image forming apparatus
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US Patent 7681005 Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
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US Patent 7681006 Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
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US Patent 7685366 System and article of manufacture for storing data
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US Patent 7689792 Data replication in a storage system
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US Patent 7694071 Disk drives and methods allowing configurable zoning
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US Patent 7698528 Shared memory pool allocation during media rendering
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US Patent 7707357 Storage control system and method having first and second channel control sections which convert file level data to block level data, judge whether block level data is to be stored in external storage and identifies save destination address of file level data based on metadata
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US Patent 7707393 Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
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US Patent 7711913 System and method for backing up extended copy commands
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US Patent 7720802 Reclaiming resident buffers when a reclaim threshold has been exceeded by swapping the oldest in use buffer and a new buffer, and referencing the new buffer via an updated set of read and write pointers
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US Patent 7730268 Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory
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US Patent 7739241 Implementing dynamic copy-on-write (COW) storage compression through purge function
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US Patent 7743223 Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
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US Patent 7752170 Implementing dynamic copy-on-write (COW) storage compression in COW storage through zero and deleted blocks
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US Patent 7753281 System and method of updating a first version of a data file in a contactless flash memory device
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US Patent 7774094 Selecting a source cluster by measuring system factors, calculating a mount-to-dismount lifespan, and selecting the source cluster in response to the lifespan and a user policy
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US Patent 7774392 Non-volatile memory with management of a pool of update memory blocks based on each block's activity and data order
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US Patent 7779056 Managing a pool of update memory blocks based on each block's activity and data order
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US Patent 7779296 Storing data replicas remotely
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US Patent 7783827 Data processor having a memory controller with cache memory
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US Patent 7788453 Redirection of storage access requests based on determining whether write caching is enabled
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US Patent 7793065 System and method for dynamic sizing of cache sequential list
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US Patent 7802060 Hardware control for changing the operating mode of a memory
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US Patent 7818490 Partial block data programming and reading operations in a non-volatile memory
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US Patent 7818508 System and method for achieving enhanced memory access capabilities
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US Patent 7818533 Storing location identifier in array and array pointer in data structure for write process management
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US Patent 7822791 Method and apparatus for flash memory reclaim
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US Patent 7822922 Accessing data storage systems without waiting for read errors
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US Patent 7822925 Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
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US Patent 7822928 Storage device and storage device data life cycle control method
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US Patent 7822938 System and method for performing garbage collection based on unmanaged memory allocations
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US Patent 7827362 Systems, apparatus, and methods for processing I/O requests
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US Patent 7831578 Apparatus for file system management with virtual file name
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US Patent 7840765 RDMA copy-on-write
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US Patent 7840772 Physical memory control using memory classes
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US Patent 7849277 Bank controller, information processing device, imaging device, and controlling method
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US Patent 7856531 Adaptive cache sizing by utilizing regenerative entries
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US Patent 7861052 Computer system having an expansion device for virtualizing a migration source logical unit
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US Patent 7865672 Electronic system with first and second electronic units electrically communicable with each other
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US Patent 7865682 Remote copy system
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US Patent 7865761 Accessing multiple non-volatile semiconductor memory modules in an uneven manner
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US Patent 7877555 Power-aware RAM processing
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US Patent 7886112 Methods and apparatus for providing simultaneous software/hardware cache fill
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US Patent 7886126 Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system
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US Patent 7890673 System and method for accessing non processor-addressable memory
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US Patent 7890715 Suspension of an asynchronous remote copy pair system having a primary controller and a remote controller
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US Patent 7895393 RAID system and the operating method for the same
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US Patent 7895398 System and method for dynamically adjusting the caching characteristics for each logical unit of a storage array
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US Patent 7903684 Communications architecture for transmission of data between memory bank caches and ports
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US Patent 7908449 Data replication in a storage system
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US Patent 7908453 Semiconductor device having a dynamically reconfigurable circuit configuration
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US Patent 7913041 Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint
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US Patent 7913097 Fiscal data recorder programmed to write only non-blank values to memory
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US Patent 7916554 Multi-bank memory accesses using posted writes
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US Patent 7917676 Efficient execution of memory barrier bus commands with order constrained memory accesses
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US Patent 7921183 Communication system, storage device, and control device for accessing external file data on a page unit or sector unit basis
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US Patent 7921249 Weakly ordered processing systems and methods
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US Patent 7944805 Method of and apparatus for recording data on write-once disc and write-once disc therefor
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US Patent 7949831 Maintaining cache coherence using load-mark metadata to deny invalidation of load-marked cache lines
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US Patent 7958287 Semiconductor storage device and method of controlling the same
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US Patent 7958288 Semiconductor storage device and method of controlling the same
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US Patent 7962704 Storage system of storage hierarchy devices and a method of controlling storage hierarchy devices based on a user policy of I/O performance and power consumption
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US Patent 7979642 Managing the storage of high-priority storage items in storage units in multi-core and multi-threaded systems using history storage and control circuitry
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US Patent 7979645 Multiprocessor system for memory mapping of processing nodes
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US Patent 7979664 Method, system, and article of manufacture for returning empty physical volumes to a storage pool based on a threshold and an elapsed time period
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US Patent 7996445 Block reallocation planning during read-ahead processing
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US Patent 7996483 Adaptive caching in broadcast networks
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US Patent 7996634 Memory system with controller for managing management data and reverse flag for reversing write data
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US Patent 8001307 Apparatus and a method to eliminate deadlock in a bi-directionally mirrored data storage system
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US Patent 8001337 Memory system with controller for managing management data and reverse flag for reversing write data
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US Patent 8005921 Redundant image storage system and method for PACS using archived flags
Edits on 8 Dec, 2021
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Patent primary examiner of
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US Patent 8005921 Redundant image storage system and method for PACS using archived flags
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Golden AI
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Golden AI
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Patent primary examiner of
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US Patent 7996483 Adaptive caching in broadcast networks
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Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
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US Patent 7996445 Block reallocation planning during read-ahead processing
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Golden AI
edited on 8 Dec, 2021
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US Patent 7979645 Multiprocessor system for memory mapping of processing nodes
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edited on 7 Dec, 2021
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US Patent 7958288 Semiconductor storage device and method of controlling the same
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Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
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US Patent 7958287 Semiconductor storage device and method of controlling the same
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US Patent 7921249 Weakly ordered processing systems and methods
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