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Jacob Petranek

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-47 properties)
Infobox
Patent primary examiner of
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US Patent 11170464 Low latency streaming remapping engine
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US Patent 11175923 Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions
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US Patent 11175924 Load-store unit with partitioned reorder queues with single cam port
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US Patent 11175925 Load-store unit with partitioned reorder queues with single cam port
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US Patent 11176084 SIMD instruction sorting pre-sorted source register's data elements into a first ascending order destination register and a second descending destination register
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US Patent 11182156 Selectively changing arithmetic data types used in arithmetic execution of deep learning applications based on expressible ratio and fluctuation value comparisons to threshold values
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US Patent 11182200 Streaming engine with short cut start instructions
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US Patent 7783867 Controlling instruction execution in a processing environment
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US Patent 7783869 Accessing branch predictions ahead of instruction fetching
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US Patent 7805595 Data processing apparatus and method for updating prediction data based on an operation's priority level
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US Patent 7818550 Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system
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US Patent 7827385 Effecting a broadcast with an allreduce operation on a parallel computer
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US Patent 7831801 Direct memory access-based multi-processor array
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US Patent 7831802 Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine
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US Patent 7831803 Executing multiple instructions multiple date (‘MIMD’) programs on a single instruction multiple data (‘SIMD’) machine
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US Patent 7831805 Coupling a general purpose processor to an application specific instruction set processor
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US Patent 7831807 System and method for expanding the instruction set of an instruction processor
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US Patent 7831811 System and method for managing a register-based stack of operand tags
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US Patent 7831814 Monitoring a microprocessor programme by sending time-trackable messages
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US Patent 7831817 Two-level branch prediction apparatus
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US Patent 7836286 Data processing system to calculate indexes into a branch target address table based on a current operating mode
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US Patent 7836290 Return address stack recovery in a speculative execution computing apparatus
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US Patent 7836291 Method, medium, and apparatus with interrupt handling in a reconfigurable array
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US Patent 7840779 Line-plane broadcasting in a data communications network of a parallel computer
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US Patent 7849295 Data processing apparatus and data processing method including dividing data to be processed
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US Patent 7861062 Data processing device with instruction controlled clock speed
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US Patent 7861066 Mechanism for predicting and suppressing instruction replay in a processor
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US Patent 7861071 Conditional branch instruction capable of testing a plurality of indicators in a predicate register
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US Patent 7873811 Polymorphous computing fabric
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US Patent 7873815 Digital signal processors with configurable dual-MAC and dual-ALU
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US Patent 7873818 System and method for search area confined branch prediction
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US Patent 7890734 Mechanism for selecting instructions for execution in a multithreaded processor
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US Patent 7895421 Mechanism for using performance counters to identify reasons and delay times for instructions that are stalled during retirement
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US Patent 7913062 Method of rotating data in a plurality of processing elements
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US Patent 7913065 Compression of processor instructions
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US Patent 7925865 Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection
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US Patent 7930606 Selectively debugging processor cores through instruction codes
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US Patent 7945768 Method and apparatus for nested instruction looping using implicit predicates
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US Patent 7949854 Trace unit with a trace builder
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US Patent 7949858 Multifunction hexadecimal instruction form system and program product
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US Patent 7953956 Reconfigurable circuit with a limitation on connection and method of determining functions of logic circuits in the reconfigurable circuit
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US Patent 7958335 Multiple instruction set decoding
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US Patent 7975127 Computer system for processing instructions each containing a group of operations to be executed out of order
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US Patent 7987342 Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
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US Patent 7991982 Microcomputer and encoding system for executing peripheral function instructions
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US Patent 7996658 Processor system and method for monitoring performance of a selected task among a plurality of tasks
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US Patent 8006068 Processor access to data cache with fixed or low variable latency via instructions to an auxiliary processing unit
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7991982 Microcomputer and encoding system for executing peripheral function instructions
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7987342 Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
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Golden AI
edited on 8 Dec, 2021
Edits on 7 Dec, 2021
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7958335 Multiple instruction set decoding
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7949854 Trace unit with a trace builder
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7949858 Multifunction hexadecimal instruction form system and program product
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7945768 Method and apparatus for nested instruction looping using implicit predicates
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7930606 Selectively debugging processor cores through instruction codes
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7913062 Method of rotating data in a plurality of processing elements
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7913065 Compression of processor instructions
Edits on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7890734 Mechanism for selecting instructions for execution in a multithreaded processor
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7873815 Digital signal processors with configurable dual-MAC and dual-ALU
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7873818 System and method for search area confined branch prediction
Golden AI profile picture
Golden AI
edited on 6 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7873811 Polymorphous computing fabric

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