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Kimberly McLean-Mayo

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-74 properties)
Infobox
Patent primary examiner of
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US Patent 7093084 Memory implementations of shift registers
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US Patent 7096336 Information processing system and management device
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US Patent 7107319 Method and apparatus for reducing latency and message traffic during data and lock transfer in a multi-node system
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US Patent 7111118 High performance raid mapping
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US Patent 7111120 Scalable disk array controller
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US Patent 7111140 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
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US Patent 7120747 Lower overhead shared cache invalidations
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US Patent 7120758 Technique for improving processor performance
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US Patent 7124257 Bus interface controller for determining access counts
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US Patent 7124263 Memory controller, semiconductor integrated circuit, and method for controlling a memory
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US Patent 7127563 Shared memory architecture
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US Patent 7133990 System and method for controlling access to protected data stored in a storage unit
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US Patent 7139809 System and method for providing virtual network attached storage using excess distributed storage capacity
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US Patent 7139875 Disk array apparatus and control method for disk array apparatus
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US Patent 7143247 Method and apparatus for parallel execution pipeline data storage in a computer memory
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US Patent 7146453 Reducing ABENDS through the use of second-tier storage groups
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US Patent 7162604 Multi-user virtual tape system
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US Patent 7165148 Data prefetch method for indirect references
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US Patent 7165152 Method and apparatus for managing access to storage devices in a storage system with access control
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US Patent 7167947 Memory post-write page closing apparatus and method
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US Patent 7174432 Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture
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US Patent 7181582 Unified data sets distributed over multiple I/O-device arrays
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US Patent 7185150 Architectures for self-contained, mobile, memory programming
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US Patent 7188211 Block programmable priority encoder in a CAM
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US Patent 7194573 CAM-based search engine devices having advanced search and learn instruction handling
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US Patent 7200720 System and method for efficiently performing memory intensive computations including a bidirectional synchronization mechanism for maintaining consistency of data
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US Patent 7216199 Disk control system and method
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US Patent 7219199 System and method for increasing bandwidth in a directory based high speed memory system
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US Patent 7228377 Semiconductor integrated circuit device, IC card, and mobile terminal
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US Patent 7254617 Distributed cache between servers of a network
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US Patent 7260670 Non-volatile semiconductor memory device and electric device with the same
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US Patent 7263575 Electronic control device
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US Patent 7263586 Cache coherency for multiple independent cache of a domain
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US Patent 7263591 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
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US Patent 7266642 Cache residence prediction
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US Patent 7266647 List based method and apparatus for selective and rapid cache flushes
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US Patent 7275129 Accessing multiple copies of RAM distributed throughout an ASIC/FPGA and maintaining their content consistency
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US Patent 7277983 Method and apparatus for smoothing current transients in a content addressable memory (CAM) device
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US Patent 7290088 System and method for coercion of disk drive size for use in a RAID volume
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US Patent 7308536 System bus read data transfers with data ordering control bits
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US Patent 7308544 Storage control apparatus, storage system, and control method for storage system
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US Patent 7313646 Interfacing of functional modules in an on-chip system
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US Patent 7315931 Method for managing an external memory of a microprocessor
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US Patent 7318140 Method and apparatus for dynamic hosting partition page assignment
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US Patent 7320053 Banking render cache for multiple access
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US Patent 7320059 Methods and apparatus for deleting content from a storage system
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US Patent 7325088 Management of indexed registers in a system on a chip
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US Patent 7334084 Disk array apparatus and control method for disk array apparatus
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US Patent 7334093 Block programmable priority encoder in a CAM
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US Patent 7337262 Adaptive read ahead method of data recorded on a sequential media readable via a variable data block size storage device
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US Patent 7337271 Context look ahead storage structures
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US Patent 7337282 Memory system and process for controlling a memory component to achieve different kinds of memory characteristics on one and the same memory component
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US Patent 7340563 Data transmission device having the shape of a standard 3.5″ disk
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US Patent 7343469 Remapping I/O device addresses into high memory using GART
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US Patent 7350030 High performance chipset prefetcher for interleaved channels
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US Patent 7350041 Methods and apparatus for managing the storage of content
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US Patent 7350044 Data move method and apparatus
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US Patent 7353318 Apparatus and method to assign addresses to plurality of information storage devices
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US Patent 7356644 Apparatus and method for providing very large virtual storage volumes using redundant arrays of disks
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US Patent 7360054 Method and apparatus for direct conveyance of physical addresses from user level code to peripheral devices in virtual memory systems
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US Patent 7363448 Data storage apparatus, data processing method, recording medium, and program
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US Patent 7363451 Load balancing of disk drives
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US Patent 7366821 High-speed memory system
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US Patent 7370083 System and method for providing virtual network attached storage using excess distributed storage capacity
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US Patent 7370140 Enhanced DRAM with embedded registers
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US Patent 7370160 Virtualizing memory type
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US Patent 7376782 Index/data register pair for indirect register access
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US Patent 7376789 Wide-port context cache apparatus, systems, and methods
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US Patent 7380085 Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
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US Patent 7389391 Memory disposition methods and systems
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US Patent 7395381 Method and an apparatus to reduce network utilization in a multiprocessor system
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US Patent 7401188 Method, device, and system to avoid flushing the contents of a cache by not inserting data from large requests
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US Patent 7404050 Method of operating a memory device, memory module, and a memory device comprising the memory module
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US Patent 7430640 Detecting when to prefetch inodes and then prefetching inodes in parallel
Edits on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7430640 Detecting when to prefetch inodes and then prefetching inodes in parallel
Edits on 30 Nov, 2021
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edited on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7395381 Method and an apparatus to reduce network utilization in a multiprocessor system
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Golden AI
edited on 30 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7389391 Memory disposition methods and systems
Edits on 30 Nov, 2021
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Golden AI
edited on 30 Nov, 2021
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Golden AI
edited on 29 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7376789 Wide-port context cache apparatus, systems, and methods
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Golden AI
edited on 29 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7376782 Index/data register pair for indirect register access
Edits on 26 Nov, 2021
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7370160 Virtualizing memory type
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Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7370140 Enhanced DRAM with embedded registers
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Golden AI
edited on 26 Nov, 2021
Golden AI profile picture
Golden AI
edited on 26 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7366821 High-speed memory system
Edits on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7363451 Load balancing of disk drives
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Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7363448 Data storage apparatus, data processing method, recording medium, and program
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Golden AI
edited on 25 Nov, 2021
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Golden AI
edited on 25 Nov, 2021
Edits on 25 Nov, 2021
Golden AI profile picture
Golden AI
edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7353318 Apparatus and method to assign addresses to plurality of information storage devices
Edits on 24 Nov, 2021
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7350044 Data move method and apparatus
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Golden AI
edited on 24 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7350041 Methods and apparatus for managing the storage of content

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