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Nghia M Doan

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
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Infobox (-81 properties)
Infobox
Patent primary examiner of
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US Patent 11171522 Wireless charging efficiency
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US Patent 11172654 Aquarium
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US Patent 11175341 Method and arrangment for classifying a voltage fault condition in an electrical storage system
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US Patent 11177681 Electronic device and method for controlling recharge of battery
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US Patent 11182523 Incremental generation of quantum circuits
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US Patent 7761827 Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions
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US Patent 7774739 Methods for adjusting shifter width of an alternating phase shifter having variable width
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US Patent 7784017 Lithography simulation method, photomask manufacturing method, semiconductor device manufacturing method, and recording medium
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US Patent 7784018 Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model
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US Patent 7788612 System, method, and computer program product for matching cell layout of an integrated circuit design
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US Patent 7797651 Verifying design isolation using bitstreams
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US Patent 7814449 Design structure for multiple source-single drain field effect semiconductor device and circuit
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US Patent 7818695 Redistribution of current demand and reduction of power and DCAP
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US Patent 7823101 Device, method, and storage for verification scenario generation, and verification device
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US Patent 7827520 Method for correcting optical proximity effect
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US Patent 7827521 Method for manufacturing semiconductor device
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US Patent 7831936 Structure for a system for controlling access to addressable integrated circuits
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US Patent 7836413 Building binary decision diagrams efficiently in a structural network representation of a digital circuit
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US Patent 7836416 Hardware-based HDL code coverage and design analysis
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US Patent 7844934 Method for designing a semiconductor integrated circuit layout capable of reducing the processing time for optical proximity effect correction
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US Patent 7853908 Algorithmic reactive testbench for analog designs
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US Patent 7853915 Interconnect-driven physical synthesis using persistent virtual routing
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US Patent 7853917 System for building binary decision diagrams efficiently in a structural network representation of a digital circuit
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US Patent 7861210 Exposure data generator and method thereof
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US Patent 7865854 Simultaneous parameter-driven and deterministic simulation with or without synchronization
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US Patent 7873925 Method and apparatus for computing test margins for at-speed testing
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US Patent 7873926 Methods for practical worst test definition and debug during block based statistical static timing analysis
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US Patent 7877717 Accurately modeling an asynchronous interface using expanded logic elements
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US Patent 7882470 Method for heuristic preservation of critical inputs during sequential reparameterization
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US Patent 7882473 Sequential equivalence checking for asynchronous verification
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US Patent 7882475 Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors
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US Patent 7882482 Layout schemes and apparatus for high performance DC-DC output stage
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US Patent 7886243 System and method for using rules-based analysis to enhance models-based analysis
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US Patent 7886244 Driving values to DC adjusted/untimed nets to identify timing problems
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US Patent 7886246 Methods for identifying failing timing requirements in a digital design
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US Patent 7886261 Programmable logic device adapted to enter a low-power mode
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US Patent 7890905 Slew constrained minimum cost buffering
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US Patent 7890915 Statistical delay and noise calculation considering cell and interconnect variations
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US Patent 7895550 On chip local MOSFET sizing
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US Patent 7895554 Verification method with the implementation of well voltage pseudo diodes
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US Patent 7904838 Circuits with transient isolation operable in a low power state
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US Patent 7904839 System and method for controlling access to addressable integrated circuits
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US Patent 7904840 Method and system to redistribute white space for minimizing wire length
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US Patent 7904841 Method and system for optimizing digital filters
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US Patent 7904842 Modifying a logic implementation by swapping inputs of fanout-free cones
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US Patent 7904844 System, method, and computer program product for matching cell layout of an integrated circuit design
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US Patent 7904845 Determining locations on a wafer to be reviewed during defect review
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US Patent 7904846 Method for automatically extracting a functional coverage model from a constraint specification
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US Patent 7904848 System and method for runtime placement and routing of a processing array
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US Patent 7904849 Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring
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US Patent 7904850 System and method for converting software to a register transfer (RTL) design
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US Patent 7904869 Method of area compaction for integrated circuit layout design
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US Patent 7904870 Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering
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US Patent 7908577 Apparatus and method for analyzing circuit specification description design
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US Patent 7913193 Determining relative amount of usage of data retaining device based on potential of charge storing device
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US Patent 7913212 Method for determining a length of shielding of a semiconductor integrated circuit wiring
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US Patent 7913213 Tool and method for automatically identifying minimum timing violation corrections in an integrated circuit design
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US Patent 7917886 Automatic system and method for providing PCB layout
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US Patent 7921389 Controlling operation of a digital system utilizing register entities
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US Patent 7925999 Method of modifying vias connection of printed circuit boards
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US Patent 7926012 Design-For-testability planner
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US Patent 7930654 System and method of correcting errors in SEM-measurements
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US Patent 7937676 Method of arranging mask patterns and apparatus using the method
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US Patent 7945868 Tunable integrated circuit design for nano-scale technologies
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US Patent 7945871 Integrated OPC verification tool
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US Patent 7954073 Methods of arranging mask patterns responsive to assist feature contribution to image intensity and associated apparatus
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US Patent 7958463 Computer automated method for manufacturing an integrated circuit pattern layout
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US Patent 7958478 Production method, design method and design system for semiconductor integrated circuit
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US Patent 7962869 Method and system for debug and test using replicated logic
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US Patent 7962872 Timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy
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US Patent 7966591 System and method for verifying race-driven registers
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US Patent 7971178 System to merge custom and synthesized digital integrated circuit design data
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US Patent 7975244 Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks
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US Patent 7979831 Placement driven control set resynthesis
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US Patent 7984399 System and method for random defect yield simulation of chip with built-in redundancy
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US Patent 7984400 Techniques for use with automated circuit design and simulations
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US Patent 7992110 Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
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US Patent 7992124 System and method for optimizing analog circuit designs
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US Patent 7996804 Signal delay skew reduction system
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US Patent 7996812 Method of minimizing early-mode violations causing minimum impact to a chip design
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US Patent 8010917 Method and system for implementing efficient locking to facilitate parallel processing of IC designs
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7996812 Method of minimizing early-mode violations causing minimum impact to a chip design
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7996804 Signal delay skew reduction system
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7992124 System and method for optimizing analog circuit designs
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7992110 Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984399 System and method for random defect yield simulation of chip with built-in redundancy
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7984400 Techniques for use with automated circuit design and simulations
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7979831 Placement driven control set resynthesis
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7971178 System to merge custom and synthesized digital integrated circuit design data
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7966591 System and method for verifying race-driven registers
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7962869 Method and system for debug and test using replicated logic
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7958478 Production method, design method and design system for semiconductor integrated circuit
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7958463 Computer automated method for manufacturing an integrated circuit pattern layout
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7945871 Integrated OPC verification tool
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7945868 Tunable integrated circuit design for nano-scale technologies
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7937676 Method of arranging mask patterns and apparatus using the method

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