SBIR/STTR Award attributes
Continuous-time digital signal processing (CT-DSP) is a promising approach for high-speed, low size-weight-and-power (SWaP) sensor signal processing in the next generation of missiles and other space- and power-constrained environments. The idea behind CT-DSP, in comparison to traditional DSP approaches, is that the digitized signal is processed without sampling; that is, the signal is processed only when the input or intermediate signals change. In order to realize the promise of CT-DSP on FPGAs and implement all the important building blocks needed for useful DSP systems, we must have robust designs for delay lines. To achieve this, we propose two designs for delay elements that can be calibrated on-chip to deliver the appropriate amount of delay and propose to test the feasibility of our delay line designs, perform simulation analysis using the measured performance of the delay line primitives to understand the trade-offs between various internal signal representations, and demonstrate their operation of our delay line designs with a proof-of-concept FIR filter implementation.
