Richard Ellis

US Patent 7376814 Method for forming variable length instructions in a processing system

US Patent 7395416 Computer processing system employing an instruction reorder buffer

US Patent 7418581 Method and apparatus for sampling instructions on a processor that supports speculative execution

US Patent 7434033 Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

US Patent 7434037 System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries

US Patent 7437539 Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

US Patent 7447883 Allocation of branch target cache resources in dependence upon program instructions within an instruction queue

US Patent 7461242 Method and apparatus for providing context switching of logic in an integrated circuit using test scan circuitry

US Patent 7473293 Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator

US Patent 7475222 Multi-threaded processor having compound instruction and operation formats

US Patent 7475226 System for managing data dependency using bit field instruction destination vector identifying destination for execution results

US Patent 7483420 DSP circuitry for supporting multi-channel applications by selectively shifting data through registers

US Patent 7484076 Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)

US Patent 7484078 Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering

US Patent 7484080 Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer

US Patent 7500089 SIMD processor with exchange sort instruction operating or plural data elements simultaneously

US Patent 7502911 Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length

US Patent 7502918 Method and system for data dependent performance increment and power reduction

US Patent 7509480 Selection of ISA decoding mode for plural instruction sets based upon instruction address

US Patent 7516305 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

US Patent 7516307 Processor for computing a packed sum of absolute differences and packed multiply-add

US Patent 7516311 Deterministic microcontroller context arrangement

US Patent 7519798 Utilizing a branch predictor outcome to decide whether to fetch or not to fetch from a branch target buffer

US Patent 7529917 Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array

US Patent 7533243 Processor for executing highly efficient VLIW

US Patent 7568088 Flag management in processors enabled for speculative execution of micro-operation traces

US Patent 7568089 Flag management in processors enabled for speculative execution of micro-operation traces

US Patent 7574583 Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor

US Patent 7587585 Flag management in processors enabled for speculative execution of micro-operation traces

US Patent 7610469 Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer

US Patent 7640422 System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache

US Patent 7653807 Removing a pipeline bubble by blocking clock signal to downstream stage when downstream stage contains invalid data

US Patent 7711763 Microprocessor instructions for performing polynomial arithmetic operations

US Patent 7725894 Enhanced un-privileged computer instruction to store a facility list

US Patent 7734901 Processor core and method for managing program counter redirection in an out-of-order processor pipeline

US Patent 7761857 Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts

US Patent 7814298 Promoting and appending traces in an instruction processing circuit based upon a bias value

US Patent 7818358 Microprocessor with random number generator and instruction for storing random data

US Patent 7818544 Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition

US Patent 7844803 Configurable data processing device with bit reordering on inputs and outputs of configurable logic function blocks

US Patent 7849120 Microprocessor with random number generator and instruction for storing random data

US Patent 7873817 High speed multi-threaded reduced instruction set computer (RISC) processor with hardware-implemented thread scheduler

US Patent 7895419 Rotate then operate on selected bits facility and instructions therefore

US Patent 7900026 Target branch prediction using a plurality of tables

US Patent 7934078 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

US Patent 7958337 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

US Patent 7979684 Method and context switch device for implementing design-for-testability functionality of latch-based register files

US Patent 7991980 Concurrent execution of instructions in a processing system