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Richard L. Ellis

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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edited on 14 Dec, 2021
Edits made to:
Infobox (-37 properties)
Infobox
Patent primary examiner of
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US Patent 7114060 Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme
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US Patent 7117346 Data processing system having multiple register contexts and method therefor
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US Patent 7136991 Microprocessor including random number generator supporting operating system-independent multitasking operation
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US Patent 7139897 Computer instruction dispatch
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US Patent 7139899 Selected register decode values for pipeline stage register addressing
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US Patent 7143266 Storing immediate data of immediate instructions in a data table
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US Patent 7149878 Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
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US Patent 7155599 Method and apparatus for a register renaming structure
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US Patent 7206926 Programmable unit including program operation unit and associated stopping device
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US Patent 7213133 Method and apparatus for avoiding write-after-write hazards in an execute-ahead processor
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US Patent 7216219 Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor
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US Patent 7219112 Microprocessor with instruction translator for translating an instruction for storing random data bytes
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US Patent 7237087 Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells
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US Patent 7257697 Processing system with general purpose execution unit and separate independently operating data string manipulation unit
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US Patent 7263603 Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor
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US Patent 7272700 Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques
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US Patent 7281120 Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
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US Patent 7296141 Method for cancelling speculative conditional delay slot instructions
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US Patent 7302552 System for processing VLIW words containing variable length instructions having embedded instruction length identifiers
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US Patent 7305543 Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations
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US Patent 7313677 Processing activity masking in a data processing system
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US Patent 7321964 Store-to-load forwarding buffer using indexed lookup
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US Patent 7331041 Method of changing modes of code generation
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US Patent 7334009 Microprocessor with random number generator and instruction for storing random data
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US Patent 7334110 Decoupled scalar/vector computer architecture system and method
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US Patent 7334116 Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length
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US Patent 7343472 Processor having a finite field arithmetic unit utilizing an array of multipliers and adders
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US Patent 7343474 Minimal address state in a fine grain multithreaded processor
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US Patent 7343478 Register window system and method that stores the next register window in a temporary buffer
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US Patent 7350054 Processor having array of processing elements whose individual operations and mutual connections are variable
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US Patent 7353364 Apparatus and method for sharing a functional unit execution resource among a plurality of functional units
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US Patent 7360060 Using IMPDEP2 for system commands related to Java accelerator hardware
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US Patent 7360070 Specialized processing upon an occurrence of an exceptional situation during the course of a computation
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US Patent 7366879 Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses
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US Patent 7380112 Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags
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US Patent 7383426 Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system
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US Patent 7523296 System and method for handling exceptions and branch mispredictions in a superscalar microprocessor
Edits on 2 Dec, 2021
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edited on 2 Dec, 2021
Edits on 30 Nov, 2021
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edited on 30 Nov, 2021
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edited on 30 Nov, 2021
Edits on 26 Nov, 2021
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edited on 26 Nov, 2021
Edits on 25 Nov, 2021
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edited on 25 Nov, 2021
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edited on 25 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7360060 Using IMPDEP2 for system commands related to Java accelerator hardware
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Golden AI
edited on 25 Nov, 2021
Edits on 24 Nov, 2021
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edited on 24 Nov, 2021
Edits on 23 Nov, 2021
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edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7343474 Minimal address state in a fine grain multithreaded processor
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Golden AI
edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7334110 Decoupled scalar/vector computer architecture system and method
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7334009 Microprocessor with random number generator and instruction for storing random data
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7331041 Method of changing modes of code generation
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7321964 Store-to-load forwarding buffer using indexed lookup
Golden AI profile picture
Golden AI
edited on 23 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7313677 Processing activity masking in a data processing system
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Golden AI
edited on 23 Nov, 2021
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Golden AI
edited on 23 Nov, 2021

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