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Tammy Thanh Nguyen

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-59 properties)
Infobox
Patent primary examiner of
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US Patent 7734826 Client-server model for synchronization of files
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US Patent 7737483 Low resistance void-free contacts
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US Patent 7745236 Floating gate process methodology
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US Patent 7745267 Method of fabricating active layer of thin film transistor
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US Patent 7745314 Method of degassing thin layer and method of manufacturing silicon thin film
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US Patent 7754517 Method for manufacturing infrared detecting device
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US Patent 7755150 MOS solid-state image pickup device and manufacturing method thereof
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US Patent 7763502 Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
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US Patent 7776632 Method for manufacturing a CMOS image sensor device
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US Patent 7781244 Method of manufacturing nitride-composite semiconductor laser element, with disclocation control
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US Patent 7781346 Methods of forming patterns and capacitors for semiconductor devices using the same
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US Patent 7785958 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
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US Patent 7786552 Semiconductor device having hydrogen-containing layer
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US Patent 7795687 MOS field effect transistor having plurality of channels
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US Patent 7803708 Method for reducing amine based contaminants
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US Patent 7811893 Shallow trench isolation stress adjuster for MOS transistor
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US Patent RE41842 Methods of forming electrical interconnects on integrated circuit substrates using selective slurries
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US Patent 7816154 Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same
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US Patent 7816222 Method for manufacturing semiconductor device having a capacitor
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US Patent 7816241 Method for preparing compound semiconductor substrate
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US Patent 7820496 Thin film transistor substrate manufactured through 3-sheet mask process, method of manufacturing the same and liquid crystal display having the same
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US Patent 7825431 Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection
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US Patent 7825451 Array of capacitors with electrically insulative rings
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US Patent 7829411 Method and device to form high quality oxide layers of different thickness in one processing step
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US Patent 7829451 Conductive ball mounting method and apparatus having a movable solder ball container
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US Patent 7838418 Spray dispensing method for applying liquid metal
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US Patent 7842578 Method for fabricating MOS devices with a salicided gate and source/drain combined with a non-silicide source drain regions
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US Patent 7851325 Strained semiconductor using elastic edge relaxation, a buried stressor layer and a sacrificial stressor layer
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US Patent 7858453 Method of manufacturing semiconductor device and display device utilizing solution ejector
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US Patent 7867863 Method for forming self-aligned source and drain contacts using a selectively passivated metal gate
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US Patent 7868363 Semiconductor component arrangement comprising a trench transistor
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US Patent 7871871 Manufacturing method for semiconductor integrated circuit device
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US Patent 7871896 Precision trench formation through oxide region formation for a semiconductor device
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US Patent 7875554 Method for electroless depositing a material on a surface of a wafer
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US Patent 7880278 Integrated circuit having stress tuning layer
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US Patent 7890575 Dynamic persistent user management in delegated environments
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US Patent 7892861 Method for fabricating a compound-material wafer
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US Patent 7892918 Method of fabricating a semiconductor device including formation of contact holes
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US Patent 7906388 Semiconductor device and method for manufacture
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US Patent 7919348 Methods for protecting imaging elements of photoimagers during back side processing
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US Patent 7927890 Method of manufacturing a semiconductor device
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US Patent 7927920 Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package
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US Patent 7943516 Manufacturing method for semiconductor device
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US Patent 7943931 Array substrate having a supporter for a data pad, and display apparatus having the array substrate
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US Patent 7943982 Semiconductor device having laminated electronic conductor on bit line
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US Patent 7951660 Methods for fabricating a metal-oxide-semiconductor device structure
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US Patent 7951662 Method of fabricating strained silicon transistor
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US Patent 7951673 Forming abrupt source drain metal gate transistors
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US Patent 7964450 Wirebondless wafer level package with plated bumps and interconnects
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US Patent 7972910 Manufacturing method of integrated circuit device including thin film transistor
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US Patent 7977779 Mountable integrated circuit package-in-package system
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US Patent 7989845 Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof
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US Patent 7993966 Method for manufacturing silicon carbide semiconductor device having high channel mobility
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US Patent 7994575 Metal-oxide-semiconductor device structures with tailored dopant depth profiles
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US Patent 7998800 Method for manufacturing semiconductor device
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US Patent 7998863 High efficiency solar cell fabrication
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US Patent 8003486 Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layer
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US Patent 8008211 Pattern forming method, semiconductor device manufacturing apparatus and storage medium
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US Patent 8012825 Method of manufacturing the double-implant nor flash memory structure
Edits on 13 Dec, 2021
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Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 8012825 Method of manufacturing the double-implant nor flash memory structure
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 8008211 Pattern forming method, semiconductor device manufacturing apparatus and storage medium
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7998863 High efficiency solar cell fabrication
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7998800 Method for manufacturing semiconductor device
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Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7994575 Metal-oxide-semiconductor device structures with tailored dopant depth profiles
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Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7977779 Mountable integrated circuit package-in-package system
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7972910 Manufacturing method of integrated circuit device including thin film transistor
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7964450 Wirebondless wafer level package with plated bumps and interconnects
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7951673 Forming abrupt source drain metal gate transistors
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7951662 Method of fabricating strained silicon transistor
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Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7951660 Methods for fabricating a metal-oxide-semiconductor device structure
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7943982 Semiconductor device having laminated electronic conductor on bit line
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7943516 Manufacturing method for semiconductor device
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Golden AI
edited on 7 Dec, 2021
Golden AI profile picture
Golden AI
edited on 7 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7927890 Method of manufacturing a semiconductor device

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