US Patent 10002671 Semiconductor memory device

A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.