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US Patent 10003346 Fractional PLLs with low correlation

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
March 20, 2015
Date of Patent
June 19, 2018
Patent Application Number
15556335
Patent Citations Received
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US Patent 10461917 Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
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US Patent 10771066 Phase locked loop, phase locked loop arrangement, transmitter and receiver and method for providing an oscillator signal
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US Patent 10541737 Phase locked loop, phase locked loop arrangement, transmitter and receiver and method for providing an oscillator signal
‌
US Patent 11757609 Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
‌
US Patent 11044071 Serializer/Deserializer (SerDes) lanes with lane-by-lane datarate independence
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US Patent 10291386 Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10003346
Patent Primary Examiner
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Sanh Phu

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