US Patent 10013212 System architecture with memory channel DRAM FPGA module

An accelerator controller comprises a detector and a loader. The detector detects runtime features of an application or a virtual machine and identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features. The loader loads the identified accelerator logic into at least one dynamic random access memory (DRAM). The at least one DRAM array is selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic, and the at least one DRAM array is in a cache-coherent address space of the operating system environment. The accelerator logic may comprise a look-up table (LUT).