Patent attributes
Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2N cells for both normal and self refresh operation modes.
