US Patent 10025531 Reducing read command latency in storage devices

A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.