Patent attributes
Systems and methods for improving the performance of a non-volatile memory array during a memory operation by concurrently applying two different selected word line voltages to two different word lines within the non-volatile memory array are described. The memory operation may comprise a write operation or a combination of SET and RESET operations. The memory array may include a first word line connected to a first set of memory cells, a second word line connected to a second set of memory cells, and a third word line connected to a third set of memory cells. During the memory operation, the first word line may be set to a first selected word line voltage (e.g., 3V), the second word line may be set to a second selected word line voltage (e.g., 0V), and the third word line may be set to an unselected word line voltage (e.g., 1.5V).
