Patent attributes
Provided are an NOR gate circuit, a shift register, an array substrate and a display apparatus, wherein the NOR gate circuit comprises a first inverter and a second inverter, each of the first inverter and the second inverter having an input terminal (VIN), a high voltage terminal (VGH), a low voltage terminal (VGL) and an output terminal (VOUT), the output terminal (VOUT) of the first inverter being connected to the high voltage terminal (VGH) of the second inverter, and wherein at least one of the first inverter and the second inverter comprises: a first transistor (T1; T5) having a gate connected to a first node (VA), a first electrode connected to the high voltage terminal (VGH) and a second electrode connected to the output terminal (VOUT), a first capacitor (C1; C2) having a first terminal connected to the first node (VA) and a second terminal connected to the output terminal (VOUT), a pulling-up module being configured to pull up a potential at the first node (VA) by a potential at the high voltage terminal (VGH) in a case where the high voltage terminal (VGH) is at a high level, and a pulling-down module being configured to pull down a potential at the first node (VA) and a potential at the output terminal (VOUT) by a potential at the low voltage terminal (VGL) under a control of a signal received by the input terminal (VIN). The threshold loss existing in the NOR gate circuit formed by an Oxide TFT can be eliminated.
