Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Chia-Jung Chen0
Chun-Hsiung Hung0
Date of Patent
July 24, 2018
0Patent Application Number
155993500
Date Filed
May 18, 2017
0Patent Citations Received
Patent Primary Examiner
Patent abstract
For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected set of N bit lines in the plurality of bit lines, write logic is coupled to the set of write drivers which enables a permissible number less than said number N of said members of the set of write drivers to apply a write pulse in parallel in a write operation. The write logic can dynamically assign permissible numbers to iterations in an iterative write sequence. A power source, such as charge pump circuitry, coupled to the set of write drivers can be utilized more efficiently in systems applying permissible bit write logic, enabling higher throughput or utilizing lower peak power.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.