US Patent 10043459 Display timing controller with single-frame buffer memory

A display device includes a display timing controller to effect interlaced writing of images to a display panel. The display timing controller includes a single-frame buffer memory and is configured to, during a first frame write time, write odd row image data from odd row memory locations to odd rows of pixels of the display device while simultaneously storing even row image data into even row memory locations while abstaining from overwriting the odd row data. At a second frame write time, the display timing controller writes even row image data from the even row memory locations to the even rows of pixels of the display device while simultaneously storing odd row image data into odd row memory locations while abstaining from overwriting odd row image data.