US Patent 10056150 Non-volatile semiconductor memory device

According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.