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US Patent 10062752 Fabrication of nanowire vertical gate devices
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Patent
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Date Filed
October 25, 2017
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Date of Patent
August 28, 2018
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Patent Application Number
15793566
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Patent Citations Received
US Patent 11387234 Semiconductor device
US Patent 10811528 Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs
US Patent 10971367 Method for fabricating vertical transistor having a silicided bottom
US Patent 11769822 Semiconductor device and method for manufacturing the same
US Patent 11380791 Semiconductor device
US Patent 10755937 Vertical transistor having a silicided bottom and method for fabricating thereof
US Patent 10797138 Vertical-transport field-effect transistors with self-aligned contacts
Patent Inventor Names
Effendi Leobandung
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10062752
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Patent Primary Examiner
Karen Kusumakar
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