US Patent 10063303 Fast memory access control for phase and gain

An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a plurality of control signals in response to an enable signal. One control signal at a time may be active while the enable signal is in a transfer state. The registers may be configured to (i) buffer a plurality of setting values received from a memory and (ii) present the setting values from a subset of the registers to a plurality of transceiver circuits while a corresponding control signal is active. The setting values may include a plurality of phase values and a plurality of gain values used in the transceiver circuits to steer a radio frequency beam. Each transceiver channel may update the setting values from the registers within a predetermined time after a corresponding control signal becomes active.