US Patent 10068970 Nanowire isolation scheme to reduce parasitic capacitance

A method for manufacturing a semiconductor device includes forming a doped silicon layer on a bulk substrate, forming an undoped silicon cap layer on the doped silicon layer, forming a stacked configuration of silicon germanium (SiGe) and silicon layers on the undoped silicon cap layer, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on an SiGe layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, the doped silicon layer and the undoped silicon cap layer, forming a spacer layer on each of the plurality of dummy gates, and on the doped silicon layer and the undoped silicon cap layer, selectively etching the doped silicon layer with respect to the undoped silicon layer, and filling the area from where the doped s silicon layer was selectively removed with a dielectric layer.