Log in
Sign up
Golden has been acquired by ComplyAdvantage.Read about it here ⟶
‌

US Patent 10074423 Impedance tuning between packaging and dies

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
March 8, 2017
0
Date of Patent
September 11, 2018
0
Patent Application Number
15453418
0
Patent Citations Received
‌
US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
0
‌
US Patent 11836102 Low latency and high bandwidth artificial intelligence processor
0
‌
US Patent 11844223 Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
0
‌
US Patent 12001266 Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic
0
‌
US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging
0
‌
US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic
0
‌
US Patent 10446200 Memory device with configurable input/output interface
‌
US Patent 10541010 Memory device with configurable input/output interface
Patent Inventor Names
Nimrod Hermesh
0
Eliran Kanza
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
10074423
0
Patent Primary Examiner
‌
Jason Lappas
0

Find more entities like US Patent 10074423 Impedance tuning between packaging and dies

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo