US Patent 10074664 Semiconductor memory device including slimming structure

Disclosed is a semiconductor memory device, including: a slimming structure extended from a cell structure in a direction parallel to the semiconductor substrate, the cell structure having a plurality of cell transistors stacked over a semiconductor substrate; vertical insulating materials extended in a direction crossing the semiconductor substrate and configured to divide the cell structure and the slimming structure into a plurality of memory blocks; contact plugs passing through the vertical insulating materials, respectively, within an area in which the slimming structure is formed; and junctions formed within the semiconductor substrate under the vertical insulating materials, in which the junctions are coupled to the contact plugs, respectively.