Patent attributes
An external circuit element RSET is connected in use to an SET terminal. A synchronous rectification controller generates a pulse signal S1 based on a control time determined according to the state of the SET terminal. A driver switches on and off the synchronous rectification transistor according to the pulse signal S1. An abnormal state detection circuit is capable of detecting an open-circuit state and/or a short-circuit state that can occur in the SET terminal. When the abnormal state detection circuit detects such an open-circuit state and/or short-circuit state, the abnormal state detection circuit asserts a detection signal S11. When the detection signal S11 is asserted, a primary-side controller arranged on the primary side of the DC/DC converter is instructed to suspend the switching operation of a switching transistor.
