Patent attributes
A receiving device includes a first calculating circuit, an error slicer, a data slicer, a second calculating circuit, and an equalization circuit. The first calculating circuit is configured to generate a calculating signal according to an equalized signal and a feedback signal. The error slicer is configured to generate an error signal according to the calculating signal. The data slicer is configured to generate a data signal according to the calculating signal. The second calculating circuit is configured to generate a first, a second, and a third equalization coefficient according to the data signal and the error signal. The equalization circuit is configured to generate the feedback signal according to the first, the second, and the third equalization coefficient. A gain value of the equalization circuit is associated with the first equalization coefficient. A time constant of the equalization circuit is associated with the second and the third equalization coefficient.