Patent attributes
An reciprocal quantum logic (RQL) gate circuit has an input stage having logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and an amplifying output stage comprising a JTL to deliver an output signal. The input stage includes two or more storage loops, at least two being associated each with a logical input, each comprising an input Josephson junction (JJ), a storage inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a bias signal provided to the circuit. The output stage asserts an output based on the triggering of the logical decision JJ.
