US Patent 10109368 Pulse output circuit, shift register and display device

A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.