US Patent 10114795 Processor in non-volatile storage memory

In one example, a device includes a non-volatile memory divided into a plurality of selectable locations, wherein the selectable locations are grouped into a plurality of data lines; one or more processing units (PUs) coupled to the non-volatile memory, each of the PUs associated with a data line of the plurality of data lines, the one or more processing units comprising one or more reconfigurable PUs, the one or more PUs configured to: manipulate, based on one or more instruction sets, data in an associated data line to generate results that are stored in selectable locations of the associated data line reserved to store results of the manipulation; determine which of the instruction sets are most frequently used by the one or more PUs to manipulate data; and reconfigure the one or more reconfigurable PUs to manipulate data using the determined most frequently used instruction sets.