Patent attributes
A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.
