Patent attributes
Various embodiments of fractional-N phase-locked loop (PLL) frequency synthesizers based on digital-to-analog conversion (DAC) are disclosed. In some embodiments, a PLL frequency synthesizer includes a phase-frequency detector, a voltage controlled oscillator (VCO) coupled to the phase-frequency detector, and a digital-to-analog converter (DAC) coupled between an input of the phase-frequency detector and an output of the VCO within a feedback path of the PLL frequency synthesizer. The phase-frequency detector is configured to receive a reference input clock and an output signal of the DAC as a feedback input clock. Furthermore, the DAC receives an output clock from the VCO and a digital control signal comprising frequency and phase information for synthesizing the feedback input clock. The disclosed DAC-based PLL frequency synthesizers do not require any frequency divider in a feedback path of the PLL, thereby significantly reducing power consumption and noise levels.
