Patent attributes
A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vglitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vtrip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage Vbias, wherein Vbias is chosen such that either both conditions (Vbias<Vtrip) and (Vbias+Vglitch>Vtrip) or both conditions (Vbias>Vtrip) and (Vbias−Vglitch<Vtrip) are always true.
