US Patent 10157258 Method for evaluating failure-in-time
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Patent abstract
A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.
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Patent Inventor Names
Chin-Shen Lin0
Chung-Hsing Wang0
Kuo-Nan Yang0
Ming-Hsien Lin0
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US Patent 10157258 Method for evaluating failure-in-time
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Patent jurisdiction
Patent number
10157258
Date of patent
December 18, 2018
Patent application number
15355410
Date Filed
November 18, 2016
Patent primary examiner
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