US Patent 10157919 Device for a FinFET

A semiconductor device includes a semiconductor substrate, multiple fins formed on a front surface of the semiconductor substrate, a stress layer formed on a top surface of the fins, multiple strip-shaped gate structures formed above the stress layers, each of which extending in a direction substantially perpendicular to a direction of the fins, a contact hole etch stop layer covering the front surface of the semiconductor substrate, sidewalls of the fins, and top surfaces and sidewalls of the stress layers, a first interlayer dielectric layer over the contact hole etch stop layer, the first interlayer dielectric layer including filling voids formed therein, and a top surface of the first interlayer dielectric layer being below the top surfaces of the stress layers, a barrier liner layer over the first interlayer dielectric layer, and a second interlayer dielectric layer over the barrier liner layer and the contact hole etch stop layer.