US Patent 10162005 Scan chain operations

A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.