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US Patent 10163756 Isolation structure for stacked dies

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
April 16, 2014
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Date of Patent
December 25, 2018
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Patent Application Number
14254597
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Patent Citations Received
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US Patent 12112997 Micro through-silicon via for transistor density scaling
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US Patent 11652026 Micro through-silicon via for transistor density scaling
0
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US Patent 11393741 Micro through-silicon via for transistor density scaling
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US Patent 12080628 Micro through-silicon via for transistor density scaling
0
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US Patent 11476176 Semiconductor device having via protective layer
Patent Inventor Names
Chen-Hua Yu
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Chen-Shien Chen
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Hung-Pin Chang
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Kuo-Ching Hsu
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Wen-Chih Chiou
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10163756
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Patent Primary Examiner
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Lex Malsawma
0

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