US Patent 10177252 Semiconductor device isolation with RESURF layer arrangement

A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact.