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US Patent 10180692 Semiconductor device

Patent 10180692 was granted and assigned to Toshiba Memory Corporation on January, 2019 by the United States Patent and Trademark Office.

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Patent Citations Received
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US Patent 11881454 Stacked IC structure with orthogonal interconnect layers
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Patent abstract

A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.

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US Patent 11790219 Three dimensional circuit implementing machine trained network
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Patent Inventor Names
Toshiyuki Kouchi0
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US Patent 11557516 3D chip with shared clock distribution network
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Infobox
Is a
Patent
Patent
0
Patent Applicant
Toshiba Memory Corporation
Toshiba Memory Corporation
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Current Assignee
Toshiba Memory Corporation
Toshiba Memory Corporation
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
101806920
Date of Patent
January 15, 2019
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Patent Application Number
148337120
Date Filed
August 24, 2015
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Patent Citations Received
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US Patent 10970627 Time borrowing between layers of a three dimensional chip stack
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US Patent 11289333 Direct-bonded native interconnects and active base die
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Patent Primary Examiner
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Tim T Vo
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Patent citations received
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US Patent 11289333 Direct-bonded native interconnects and active base die
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US Patent 10970627 Time borrowing between layers of a three dimensional chip stack
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 US Patent 10180692 Semiconductor device

Infobox
Is a
Patent
Patent
Patent applicant
Toshiba Memory Corporation
Toshiba Memory Corporation
Current assignee
Toshiba Memory Corporation
Toshiba Memory Corporation
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10180692
Date of patent
January 15, 2019
Patent application number
14833712
Date Filed
August 24, 2015
Patent primary examiner
‌
Tim T Vo

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