US Patent 10180919 Broadcasting reads to multiple modules

A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.