Patent attributes
Package substrate and a method of manufacturing the same is disclosed. The package substrate includes an insulating layer having first circuit patterns embedded in a first surface of the insulating layer, and a protruded circuit pattern formed above at least one of the embedded first circuit patterns, wherein a width of the protruded circuit pattern is greater than a width of each of the embedded first circuit patterns. Accordingly, a flip chip and a wire bonding chip may be installed at the same time owing to an embedded structure of circuit pattern and a protruded structure of circuit pattern realized together on a surface where an electronic component is to be installed. Moreover, a fine circuit pattern may be formed, and a surface treatment layer may be selectively formed at desired portions without forming an additional seed layer for electroplating, thereby possibly simplifying manufacturing processes and saving manufacturing costs.
