US Patent 10181856 Digital phase locked loop frequency estimation
Patent 10181856 was granted and assigned to Intel on January, 2019 by the United States Patent and Trademark Office.
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Patent abstract
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.
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Patent Inventor Names
Ashoke Ravi0
Elan Banin0
Nati Dinur0
Ran Shimon0
Roy Amel0
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Patent Jurisdiction
Patent Number
101818560
Date of Patent
January 15, 2019
0Patent Application Number
153955040
Date Filed
December 30, 2016
0Patent Citations Received
Patent Primary Examiner
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US Patent 10181856 Digital phase locked loop frequency estimation
Infobox
Is a
Patent applicant
Current assignee
Patent jurisdiction
Patent number
10181856
Date of patent
January 15, 2019
Patent application number
15395504
Date Filed
December 30, 2016
Patent primary examiner
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