Patent attributes
This application relates to methods and apparatus for phase locked loops. A phase-and-frequency detector (101) receives a reference clock signal (CKref) and a feedback signal (SFB) and outputs a first adjustment signal (U) that is modulated between respective first and second signal levels to provide control pulses indicating that an increase in frequency required for phase and frequency lock, and a second adjustment signal (D) that is modulated between respective first and second signal levels to provide control pulses indicating that a decrease in frequency required for phase and frequency lock. First and second time-to-digital converters (201-1 and 201-2) receive the first and second adjustment signals respectively and output respective first and second digital signals indicative of the duration of said control pulses. Each time-to-digital converter comprises a controlled-oscillator (401, 801) configured so as to operate at a first frequency when the respective adjustment signal is at the first signal level and operate at a second frequency when the respective adjustment signal is at the second signal level and a counter (403) configured to produce a count value of the number oscillations of the controlled-oscillator in each of a succession of count periods defined by a count clock signal. The first and second digital signals are based on the count values output from the respective counters. The difference between the first and second digital signals may be determined and input to digital loop filter (203) before driving numerically-controlled-oscillator (204) to produce the output signal.
