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US Patent 10204852 Circuit substrate and semiconductor package structure
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Patent
Date Filed
February 3, 2017
Date of Patent
February 12, 2019
Patent Application Number
15423788
Patent Citations Received
US Patent 12094828 Eccentric via structures for stress reduction
0
US Patent 11670601 Stacking via structures for stress reduction
0
US Patent 11749644 Semiconductor device with curved conductive lines and method of forming the same
US Patent 11855008 Stacking via structures for stress reduction
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10204852
Patent Primary Examiner
Xiaoliang Chen
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